The present invention relates to a semiconductor integrated circuit, and more particularly, it relates to a logic circuit.
In recent semiconductor integrated circuits, a high operation speed, area reduction, small power consumption and the like have been realized by refining the fabrication processes. When the gate length of a transistor is reduced by refining the process, a drain current per unit gate width of the transistor flowing when the transistor is in an on state is advantageously increased. On the other hand, a leakage current flowing between the drain and the source when the transistor is in an off state (hereinafter referred to as the subthreshold current) is disadvantageously increased. The increase ratio of the subthreshold current involved in the refinement is larger than the increase ratio of the drain current flowing when the transistor is in an on state.
FIG. 11 is a circuit diagram for showing an example of conventional dynamic semiconductor integrated circuits. The circuit of FIG. 11 includes PMOS transistors 2101 and 2102, an input circuit 2120 and an output circuit 2130. The input circuit 2120 includes NMOS transistors 2121 and 2122, and the output circuit 2130 includes a PMOS transistor 2131 and an NMOS transistor 2132. The circuit of FIG. 11 obtains and outputs a logical OR between input signals VI1 and VI2.
A period when a clock signal CLK is at xe2x80x9cLxe2x80x9d level (namely, at a low logic level) corresponds to a precharge period. In this period, the PMOS transistor 2101 is turned on so as to precharge a node N211. The input signals VI1 and VI2 are kept at xe2x80x9cLxe2x80x9d level.
A period when the clock signal CLK is at xe2x80x9cHxe2x80x9d level (namely, a high logic level) corresponds to an evaluation period. In this period, the input signals VI1 and VI2 are activated. When one of the input signals VI1 and VI2 undergoes a xe2x80x9cLxe2x80x9d to xe2x80x9cHxe2x80x9d transition, the node N211 is discharged, and hence, an output signal V21 undergoes a xe2x80x9cLxe2x80x9d to xe2x80x9cHxe2x80x9d transition. When both the input signals VI1 and VI2 are at xe2x80x9cLxe2x80x9d level, the node N211 is not discharged, and hence, the output signal V21 is at xe2x80x9cLxe2x80x9d level. At this point, the PMOS transistor 2102 is in an on state so as to keep the potential of the node N211 at xe2x80x9cHxe2x80x9d level.
FIG. 12 is a circuit diagram for showing an example of conventional static semiconductor integrated circuits. The circuit of FIG. 12 functions as a buffer circuit in which two stages of inverters are serially connected to each other. The circuit of FIG. 12 includes an inverter having a PMOS transistor 2231 and an NMOS transistor 2232, and an inverter having a PMOS transistor 2281 and an NMOS transistor 2282.
With respect to the dynamic circuit having the configuration shown in FIG. 11, the case where the subthreshold current flowing when a transistor is in an off state becomes too large to ignore as compared with the drain current flowing when the transistor is in an on state will now be described.
In the evaluation period, even when both the input signals VI1 and VI2 are at xe2x80x9cLxe2x80x9d level, the subthreshold current flows through the NMOS transistors 2121 and 2122. At this point, the current flows from the power supply through the PMOS transistor 2102 and the NMOS transistor 2121 or 2122 to a ground line. In this case, the potential of the node N211 is lower than supply potential VDD by a voltage Vd.
At this point, when the voltage Vd is smaller than the threshold voltage Vt (that is, a gate-source voltage obtained when a transistor is switched from an off state to an on state) of the PMOS transistor 2131, the PMOS transistor 2131 is turned off and the NMOS transistor 2132 is turned on, so that the output signal V21 can be at xe2x80x9cLxe2x80x9d level. The potential of this output signal V21 is higher than ground potential VSS. Assuming that the PMOS transistor 2131 has a resistance value R2131 and the NMOS transistor 2132 has a resistance value r2132, a shift Vdo of the potential of the output signal V21 from the ground potential VSS is VDD*r2132/(R2131+r2132).
Alternatively, when the voltage Vd is larger than the threshold voltage Vt of the PMOS transistor 2131, this transistor is turned on. Since both the PMOS transistor 2131 and the NMOS transistor 2132 are in an on state, not only the output is undefined but also a large through current unavoidably flows through these transistors.
Also in the precharge period, when the subthreshold current flows through the NMOS transistors 2121 and 2122, the potential of the node N211 becomes lower than the supply potential VDD, and hence, a similar problem occurs.
Since the subthreshold current has a property to exponentially increase against the gate-source voltage Vgs of the transistor, when the gate-source voltage Vgs of the PMOS transistor 2131 is equal to the voltage Vd, a larger current flows through this transistor than when the voltage Vgs is 0, which increases the shift Vdo of the potential of the output signal V21.
In this manner, when the subthreshold current is too large to ignore, the shift of the potential of the output signal V21, namely, DC noise to be output, becomes too large to ignore. In particular, when DC noise included in an output signal is larger than DC noise included in an input signal, this means that the DC noise is amplified.
Such a phenomenon is described in xe2x80x9cA Conditional Keeper Technique for Sub-0.13xcexc Wide Dynamic Gatesxe2x80x9d (Atila Alvandpour et. al., 2001 Symposium on VLSI Circuits Digest of Technical Papers 3-4).
When a plurality of such circuits that amplify DC noise included in an input signal are serially connected to one another, the DC noise is gradually increased, resulting in the malfunction of the circuit. Also, even when the circuit does not amplify DC noise, if the voltage Vd and the shift Vdo of the potential of the output signal V21 are large, a leakage current flowing between the power supply and the ground line is exponentially increased, and hence, the power consumed when the transistor is in an off state becomes disadvantageously large.
Also in the static circuit having the configuration shown in FIG. 12, in the case where the subthreshold current flowing when a transistor is in an off state is too large to ignore as compared with the drain current flowing when the transistor is in an on state, a similar problem occurs.
Specifically, since the subthreshold current flows through the PMOS transistor 2231, even when an input signal VI is at xe2x80x9cHxe2x80x9d level, the potential of the node N221 is higher than the ground potential VSS. Therefore, the potential of an output signal V22 is lower than the supply potential VDD, namely, the output signal V22 includes DC noise. When DC noise included in the output signal is larger than DC noise included in the input signal, this means that the DC noise is amplified. Also when a plurality of such circuits that amplify DC noise included in an input signal are serially connected to one another, the malfunction of the circuit is caused.
An object of the invention is providing a semiconductor integrated circuit for outputting a signal with small DC noise.
Specifically, the first semiconductor integrated circuit of this invention includes a first transistor for setting a first node at a first logic level in accordance with a clock signal; an input circuit for setting the first node at a second logic level different from the first logic level in accordance with an input signal; a second transistor for setting a second node at the first logic level when the first node is at the first logic level; a first resistor device that is connected between the first node and the second node and has a large resistance value when the first node is at the first logic level and has a small resistance value when the first node is at the second logic level; a first driving transistor for receiving, as an input, potential of the second node and controlling whether or not an output node is set at the first logic level; and a second driving transistor for receiving, as an input, a signal at a logic level identical to the logic level of the first node and controlling whether or not the output node is set at the second logic level.
In this semiconductor integrated circuit, owing to the first resistor device, the absolute value of the gate-source voltage of the first driving transistor in an off state can be made small. Therefore, in a dynamic circuit operated in synchronization with a clock signal, the subthreshold current of the first driving transistor can be reduced, so that DC noise included in an output signal can be reduced.
In the first semiconductor integrated circuit, the second transistor preferably sets the second node at the first logic level in accordance with the clock signal.
The first semiconductor integrated circuit preferably further includes an inverter for inverting the logic level of the first node and outputting the inverted logic level, and the second transistor preferably receives, as an input, an output signal of the inverter and sets the second node at the first logic level when the first node is at the first logic level.
The first semiconductor integrated circuit preferably further includes a third transistor that receives, as an input, potential of the output node and sets the second node at the first logic level when the output node is at the second logic level.
The first semiconductor integrated circuit preferably further includes a third transistor that receives, as an input, potential of the output node and sets the first node at the first logic level when the output node is at the second logic level.
The first semiconductor integrated circuit preferably further includes an inverter for inverting the logic level of the first node and outputting the inverted logic level; and a third transistor that receives, as an input, an output signal of the inverter and keeps a logic level of the first node when the first node is at the first logic level.
The first semiconductor integrated circuit preferably further includes a third driving transistor that receives, as an input, potential of the first node and controls whether or not the output node is set at the first logic level.
In the first semiconductor integrated circuit, the first resistor device is preferably a transistor whose gate and drain are connected to each other.
The first semiconductor integrated circuit preferably further includes an inverter for inverting the logic level of the first node and outputting the inverted logic level; a third transistor that receives, as an input, an output signal of the inverter and sets a third node at the second logic level when the first node is at the second logic level; and a second resistor device that is connected between the first node and the third node and has a small resistance value when the first node is at the first logic level and has a large resistance value when the first node is at the second logic level, and the second driving transistor preferably receives, as an input, potential of the third node.
Thus, owing to the second resistor device, the absolute value of the gate-source voltage of the second driving transistor in an off state can be made small. Therefore, the subthreshold current of the second driving transistor can be reduced, so that DC noise included in the output signal can be reduced.
The first semiconductor integrated circuit preferably further includes a third driving transistor that receives, as an input, potential of the first node and controls whether or not the output node is set at the second logic level.
In the first semiconductor integrated circuit, the second resistor device is preferably a transistor whose gate and drain are connected to each other.
The first semiconductor integrated circuit preferably further includes a third transistor that receives the clock signal as an input, is connected in series to the input circuit and is turned on when the clock signal is at the first logic level.
Preferably, the first semiconductor integrated circuit is plural in number, and the first and second driving transistors included in the plural semiconductor integrated circuits together construct one logic circuit.
The second semiconductor integrated circuit of this invention includes a first transistor for setting a first node at a first logic level when an input node is at the first logic level; a first resistor device that is connected between the input node and the first node and has a large resistance value when the input node is at the first logic level and has a small resistance value when the input node is at a second logic level different from the first logic level; a first driving transistor for receiving, as an input, potential of the first node and controlling whether or not an output node is set at the first logic level; and a second driving transistor for receiving, as an input, a signal at a logic level identical to the logic level of the input node and controlling whether or not the output node is set at the second logic level.
In this semiconductor integrated circuit, owing to the first resistor device, the absolute value of the gate-source voltage of the first driving transistor in an off state can be made small. Therefore, the subthreshold current of the first driving transistor can be reduced, so that DC noise included in an output signal can be reduced.
The second semiconductor integrated circuit preferably further includes an inverter for inverting the logic level of the input node and outputting the inverted logic level, and the first transistor preferably receives, as an input, an output signal of the inverter and sets the first node at the first logic level when the input node is at the first logic level.
The second semiconductor integrated circuit preferably further includes a third driving transistor for receiving, as an input, potential of the input node and controlling whether or not the output node is set at the first logic level.
In the second semiconductor integrated circuit, the first resistor device is preferably a transistor whose gate and drain are connected to each other.
The second semiconductor integrated circuit preferably further includes an inverter for inverting the logic level of the input node and outputting the inverted logic level; a second transistor for receiving, as an input, an output signal of the inverter and setting the second node at the second logic level when the input node is at the second logic level; and a second resistor device that is connected between the input node and the second node and has a small resistance value when the input node is at the first logic level and has a large resistance value when the input node is at the second logic level, and the second driving transistor preferably receives, as an input, potential of the second node.
The second semiconductor integrated circuit preferably further includes a third driving transistor for receiving, as an input, potential of the input node and controlling whether or not the output node is set at the second logic level.
In the second semiconductor integrated circuit, the second resistor device is preferably a transistor whose gate and drain are connected to each other.
Preferably, the second semiconductor integrated circuit is plural in number, and the first and second driving transistors included the plural semiconductor integrated circuits together construct one logic circuit.
In the first or second semiconductor integrated circuit, it is preferred that the first logic level corresponds to a high logic level and that the second logic level corresponds to a low logic level.
In the first or second semiconductor integrated circuit, it is preferred that the first logic level corresponds to a low logic level and that the second logic level corresponds to a high logic level.